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[VHDL-FPGA-Verilog] pci_core.tar

Description: vhdl 写的 PCI IP核程序，已经过测试-pci ip core
Platform: | Size: 23552 | Author: planet1997 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[Other] I2C

Description: IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
Platform: | Size: 448512 | Author: shigengxin | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[VHDL-FPGA-Verilog] hssdrc_latest.tar

Description: HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
Platform: | Size: 424960 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] Altera_8051_IPcore_v1.2

Description: Alera 的8051 IP core的示例文件5个-Alera the 8051 IP core of the sample file 5
Platform: | Size: 1884160 | Author: zheng | Hits:

[VHDL-FPGA-Verilog] Quartus_fft_ip_core

Description: Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试)-Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
Platform: | Size: 299008 | Author: 刘晓彬 | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[Other] slaveController

Description: 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
Platform: | Size: 56320 | Author: shaqiu | Hits:

[VHDL-FPGA-Verilog] vga_geometry_xps92i_s3_v01_00_03

Description: Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.-Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.
Platform: | Size: 3730432 | Author: Praveen | Hits:

[VHDL-FPGA-Verilog] fft_verilog

Description: FFT IP core 源码 状态控制机-FFT IP core
Platform: | Size: 7168 | Author: chris | Hits:

[Other Embeded program] fequency

Description: 一款可用于数字频率计设计的IP核,使用该IP核科研构建基于SOPC技术的片上数字频率计，测频范围较宽。-A digital frequency meter using IP core
Platform: | Size: 203776 | Author: yzhuai | Hits:

[VHDL-FPGA-Verilog] cpu86

Description: CPU86 8086. IP core.
Platform: | Size: 436224 | Author: Tru | Hits:

[VHDL-FPGA-Verilog] spimaster

Description: SPI IP core supporting SD/MMC
Platform: | Size: 2269184 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core

Description: I2C master/slave IP core
Platform: | Size: 2180096 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] uart_serial

Description: UART IP core in VHDL
Platform: | Size: 10240 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] VERILOG-USB2.0IP-core

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
Platform: | Size: 220160 | Author: king | Hits:

[Crack Hack] tripledes

Description: 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
Platform: | Size: 31744 | Author: Yan, Like | Hits:

[VHDL-FPGA-Verilog] sdramcontroller

Description: 最完整的SDRAM控制IP核，包括源代码，仿真文件，以及IP核描述文件，包你用得上-SDRAM control of the most complete IP core, including source code, simulation, as well as IP core description files, it can be helpful
Platform: | Size: 2394112 | Author: 文武 | Hits:
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